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Author:   Scott Nelson
Company:   Harris Corporation
Date: 10/31/2012   Volume: 25-4
Abstract: Portable electronics, miniaturization, and cost reduction have been key drivers in the dramatic increase in use of bottom termination components (BTC’s) over the past several years. Similar to when the Ball Grid Array (BGA) was introduced into the market, BTC’s have brought with them new challenges and adjustments in design and assembly processes. For high reliability applications, these adjustments must be made with caution to avoid creating the potential for long term reliability issues and latent field defects.While low cost is an attractive feature of most BTC component packages, cost is typically not the driver for the use of BTC’s in low volume, high reliability electronics. Because BTC packages have the die very close to the PCB and because there are no leads extending from the sides of the package, they typically exhibit low parasitic losses due to low resistance and capacitance. Another benefit of using BTC’s on high reliability products is excellent thermal dissipation due to a relatively large component thermal pad that is attached directly to the PCB. This explains why we are seeing, and will continue to see, an increased use of bottom termination components in high reliability Aerospace and Defense applications.

With the rapid implementation of BTC’s in high reliability applicationstwo key issues have evolved. The first issue is that of improper land pattern design and the second is improper solder stencil design. Unfortunately, these two issues are at opposite extremes of the product cycle. When issues arise, this can make it difficult to answer the question, “Is it a design problem or is it a manufacturing problem?” In many cases the answer has been found to be a combination of both.

While there are numerous component packages that make up the BTC family of components, those discussed in this paper will be limited to the following industry packages: Quad Flat No-lead (QFN), Dual Flat No-lead (DFN), Small Outline No-lead (SON), and Micro Lead Frame (MLF). All of these packages are similar in construction, related by common fabrication processes, and therefore share similar design and assembly criteria.

The target audience for this paper are those that are involved in printed circuit board (PCB) design and assembly, specific but not limited to high reliability electronic circuit card assemblies (CCA’s). The intent of this paper is to provide specific BTC guidance to companies that design and/or assemble high performance electronics for applications such as aerospace and defense.

 

 

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Vanderbilt University

Engineering Capability Brief

 

Reliability of Electromechanical Systems

 

S. Mahadevan, Professor
Civil and Environmental Engineering, Vanderbilt University

VU Station B 351831, Nashville, TN 37235-1831; (615)-322-3040; fax (615)-322-3365 

email:  sankaran.mahadevan@vanderbilt.edu

 

 

Overview: The reliability of electronic devices has traditionally been estimated using experimental testing and classical statistics. Increasing complexity in modern devices and systems in recent years has led to prohibitive testing costs. Therefore, elegant and inexpensive mathematical methods that combine probability theory and optimization are becoming popular in recent years, drastically reducing testing and development costs.

 

Vanderbilt University is conducting a multi-year research effort, funded by the Sandia National Laboratories, to develop physics-based computational techniques to estimate the time-dependent reliability of electromechanical systems. The problems being addressed are reliability against stress voiding and corrosion in electronic circuits, and solder joint reliability. First-order and second-order analytical methods, as well as advanced simulation techniques are being developed.

 

Example Application: Increasing miniaturization of silicon integrated circuits in recent years has led to the observation of void initiation and growth in aluminum conductor lines of these circuits. The aluminum conductor lines are passivated with a glass layer. The thermal expansion coefficient of glass is an order of magnitude smaller than that of aluminum. The resulting growth of voids in the aluminum interconnects due to heating and cooling is a time-dependent phenomenon. Several types of variables influence this — grain size, conductor length, initial stress, void shape, stress concentration, elastic modulus, operating temperature etc.  All of these variables have uncertainties associated with them.

 

The uncertainties in the variables are modeled through statistical distributions, and combined with a stress voiding model and probabilistic analysis. The possibility of multiple void sites is also considered. The probabilistic growth of the void size with time, and the degradation of the overall aluminum liner reliability with time, are computed using several analytical and simulation techniques.

 

Other applications include corrosion and solder joint reliability modeling. The methods being investigated include first-order and second-order approximations, maximum likelihood estimation, advanced probability integration schemes, importance sampling and latin hypercube sampling, and genetic algorithms. New methods are under development for problems with multiple, highly nonlinear limit states.

 

Potential Applications: Computational probabilistic methods are increasing in popularity for the reliability estimation of a wide variety of engineering systems, due to the savings in testing and development costs. The methods provide valuable sensitivity information that helps make reliability vs. cost trade-off decisions during design. Probabilistic analysis identifies the important factors affecting reliability; this information can be used for the optimum allocation of testing resources, and to achieve robustness in design.